Analog Design & Layout Std. Cells, Memories and IOs

Analog Design & Layout

Team has in-depth expertise on variety of IPs such as SerDes (10, 16, 30 & 56 Gbps), DDRphy, USB 2.0, MIPIphy and Power management. We have also handled expanded portfolios of Data converters, clock circuits such as PLL, DLL & oscillators, Regulators, Bias, Bandgap references, Temperature sensors, UVLOs etc in almost all leading foundries at technologies varying from 500nm BCD to 3nm Finfet. Multiple full chip and IP level tape out has been successfully done with first pass silicon.

Wide range of memory with variety of architecture with top semiconductor companies has been done before. These includes Multi port memories, SRAM, Memory compilers, Register files & custom memories on cutting edge technologies.

Our team has delivered IO layout from 250nm to 3nm technologies. These includes GPIOs, LVCMOS, LVTTL, LVDS, DDR etc with Analog/Power ring. ESD resuirements for HBM, MM, CDM were taken care.

Our team has delivered multiple std cell libraries at 90nm, 65nm, 45nm, 32nm, 28nm, 22nm, 16FF, 14nm, 7nm, 3nm etc with leading foundries. These libraries include High performance, High density, 11T, 9T, 7.5T, 6T design. We are also expert when it comes to migration of libraries to latest technologies.