ASIC Design Verification

Excelmax has one of industry’s strongest teams in design verification . Our team can execute verification from scratch of complex SoC’s and IP’s by using latest methodologies such as SV-UVM, UPF and meeting key KPI such as 100% functional and code coverage Advanced  IP & SoC Verification.

Full chip verification: Proficiency in building SoC verification environment from scratch as well as legacy environment.

Module / IP Verification: Module level verification experience in wide variety of domains – Networking, Image / Video processing, x86 Processors, Bus protocols

Gate Level Simulation: Full chip gate level simulations

Low Power Verification: Expertise in low power verification methodology with CPF, UPF

Assertion Based Verification: Assertion based verification for successful and faster closure of designs using SVA & PSL

Analog & Mixed Signal Verification

The AMS verification team at Excelmax has the skillsets required to execute on:

  • Analog/mixed-signal block simulations
  • Modelling of analog and mixed signal blocks using Verilog-AMS
  • Creating digital mixed signal test benches
  • Comprehensive AMS full chip verification of mixed signal ASICs.


Multi Language Expertise:

Expertise in System Verilog, Vera, Specman E, C, C++, Verilog


Adaption of industry standard methodology for new environments using UVM/OVM/VMM. Upgrading of legacy environment to comply to UVM


Functional coverage implementation, analysis and closure. RTL Code coverage


The automation and scripting experience goes in Perl, Python, Ruby, Tcl and Shell


Directed and Constrained Random Verification