- Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
- Experience: 4-10 Years
- Work Location: Bangalore
- Work experience in Scan insertion, BIST, LBIST, MBIST – SCAN DRC/Coverage debug
- ATPG Pattern generation is must
- Gate level simulations (Zero delay/Timing Delay simulations)
- Worked on JTAG protocols, etc.
- Perl/Tcl scripting
- Timing/Formal verification/PD flow knowledge is plus.
Candidate should exhibit:
- Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
- Set aggressive goals and meet/beat the commitments.
- Flexible enough to work in a dynamic environment and multitask seamlessly.
Ability to work independently and in a team