- Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
- Experience: 4-10 Years
- Work Location: Bangalore
- He/she is responsible for micro-architecture design and development of CPU Subsystem or associated component IP like high performance Bus Architectures, Memory Controllers/ DDR/USB/ NVMe/PCIE interface etc.
- Micro-architecture development and implementation of complex IP and/or ASIC block, logic designs, and HDL code for IP/ASIC blocks.
- Working individually and sometimes leading other team members in delivery of RTL design for product features.
- Strong RTL design experience of IP designs for microcontrollers/ Microprocessors expected.
- Experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC, LEC
- Knowledge & experience of building on chip bus infrastructure using AHB or AXI based IPs/ Blocks
Candidate should exhibit:
- Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
- Set aggressive goals and meet/beat the commitments.
- Flexible enough to work in a dynamic environment and multitask seamlessly.
- Ability to work independently and in a team.