Physical Design, STA & DFT

Expertise in place & route for block build/full chip development with timing closure using industry standard tools for tasks like Synthesis, Floor Plan, Placement, CTS, Signal Integrity, IR Draw, EM, Low Power Checks and Signoff checks. Extensive Knowledge in physical verification like DRC, LVS, Antenna, Density in latest nodes like 14nm, 10nm. 7nm, 5nm, 3nm.

Physical Design

We provide support throughout RTL to GDSII stages of ASIC development flow. Our experienced team has developed advanced flows for power aware synthesis (UPF, CPF), timing constraint generation (STA), netlist floor planning for best possible PPA and place and route(PNR) for overcoming ever increasing complexity. Our engineers in-depth knowledge of EDA tools and scripting skills enable us to deliver full turn-key ASIC development.

STA (Static Timing Analysis)

STA (Static Timing Analysis) is one of the most important area in Semiconductor chip Designing. Having an in depth knowledge and exposure in STA provides opportunity in exploring and understanding how other domains operate to design chip. As expert say Timing and Performance is almost everything, STA turns out to be the single most important domain which collaborates with every other areas of chip designing. Following are some of the interesting topics that directly or indirectly falls under STA umbrella:
  • Process Variation and related Margins
  • Peripheral Interface protocols and timing
  • IR aware timing and Timing aware IR
  • Mission mode and Testmode Constraints (Data flow)
  • High Speed Clocking Architecture
  • Synchronous/Asynchronous Circuit designs
  • Signal Integrity
  • PLY (Parametric Limited Yield) and DLY (Defect Limited Yield) yield analysis of new technology nodes (Test Chips)
  • Post Silicon Debug on Performance related issues

DFT

With rising mission critical application and competition, inserting testing capability in the design stage of the chip is ever so important. Our team have expertise in developing and integrating a complete test strategy for your ASIC design to deliver high fault coverage. DFT techniques that can be applied to your design include
  • Scan Insertion
  • ATPG
  • FPGA-to-FPGA, FPGA-to-ASIC, ASIC-to-FPGA conversion
  • Test pattern generation and simulation
  • Coverage improvement
  • IDDQ
  • BIST
  • BSCAN
  • DFT Spyglass checks
  • Test mode timing constraints

Key Offerings

  • Synthesis
  • Static Timing Analysis
  • DFT
  • Test time reduction
  • Scan compression (XOR, MISR), Logic BIST
  • At speed Memory BIST & repair
  • Constraints and Timing
  • Floor planning
  • Power Grid/ IO and block placement
  • Clock Tree Synthesis
  • Stuckkat, LOC/LOS, path delay
  • Fault grading
  • Physical Verification (LVS, DRC, ERC)
  • Multi-corner Multi-mode analysis
  • Run Sign-off verification

Expertise

Technology nodes

Worked on all latest nodes 45nm, 28nm, 16nm,14nm, 10nm, 7nm.5nm, 3nm

Design Complexity

1.5 million gates to 10million gates with multiple clock domains and power domains

Fab Houses

Team has experience in working with all leading fab houses.

Tools

Worked with all popular industry standard tool flows like Synopsys, Cadence, Magma, Mentor, Apache.

Low Power

Multi power domains upto 6 domains, expertise in designing power intent, low power checks, design sanity