Job Description:

• Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
• Experience: 4-10 Years
• Work Location: Bangalore

Technical Skills:

• Memory leaf cell layout development
• Migration of layout from one tech node to another
• Block and top-level integration
• Quality and timely delivery
• EM-IR, area intensive layouts, Quality checks (QC)
• Understanding of design rules for planer and FINFET CMOS technologies
• Drive multiple projects and provide necessary technical guidance to the engineers
• Experience in developing flash memories.
• Memory Layout experience in development of low power, high performance, high density SRAM memories for 5nm to 180nm technology nodes
• The candidate must have a Bachelor or Master in (EC/ME/VLSI)
• Expertise in Custom / Compiler Memory Layout
• 7nm or below FinFet technology preferred
• Understanding of DFM and DFY checks.
• Understanding of memory compiler architectures and sub blocks.
• Knowledge of scripting in PERL/Shell/TCL/Skill is a plus.
• Strong VLSI fundamentals of semiconductor devices and physics, electrical circuits, and IC Experienced with Cadence Virtuoso/XL/Advance platform and features
• Clones, Modgen, Wire assistance, Chaining, Groups and Place and Route
• Experienced with Calibre/PVS/Assura/Hercules PV tools
• Good Verbal & written communication skills

Candidate should exhibit:

• Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
• Set aggressive goals and meet/beat the commitments.
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Ability to work independently and in a team.