Emulation

Latest Multimillion complex Design and SOCs have varying need for Emulation platforms to qualify Firmware, Performance measurements and Benchmark Analysis in pre-silicon phase before the silicon is taped out.

 The complex test and use case scenarios (which are not only time consuming and difficult in simulation environment) can be easily verified in Emulation platform. This aids in reducing the verification effort as well as enhances confidence in terms of performance, latency and benchmark analysis. This also exposes RTL and Design bugs which are difficult to reproduce in RTL verification environment.

Excelmax emulation team has successfully delivered multiple projects in Emulation domain. We at Excelmax bring expertise in latest and various Emulation platforms like Palladium from Cadence, Synopsys Zebu, Mentor Graphics Veloce emulation systems and latest Xilinx FPGA.

We have extensive experience in

  • Creation of builds for different emulation platforms
  • Pre-silicon design bring up & Device Planning
  • Establishing the flow and setup and test Automation from scratch
  • Setting up different boot flows and code for various industry CPU cores
  • Pre silicon and post silicon bring up.
  • Porting of testcases, Use-case scenarios, Benchmark to next generation and post silicon environment
  • Expertise in the Debug tool chain setup, Coresight and Trace
  • Emulation, Validation & Prototyping on FPGA & Processor-Based Platforms
  • Design Partitioning, Integration, IO & Memory Handling
  • Implementation & Timing Closure
  • Configuration & Hardware Debug

Expertise

Platforms worked for:

  • Processors- ARM, X86, Tensilica, Microblaze, Picoblaze
  • Boards- Altera, Xilinx based multi-FPGA boards
  • Emulators – Zebu, Veloce & Palladium

Tools:

  • Synthesis Tools – Xilinx Vivado, Xilinx ISE, Altera Quartus, Mentor Precision, Cadence Quiclturn
  • Partition Tools – Synopsis Certify
  • Simulation- Modelsim, Questasim, Cadence NCSim & Quickturn
  • System Debug – ARM realview ICE, Xilinx chipscope, Altera signaltap, Synopsis Identify, Debussy, J-Link, Trace-32

Protocols/ IPs:

  • PU cores- ARM, X-86, PowerPC, Tensilica
  • DDR 4 / 3 / 2
  • 0, USB3.0, OTG
  • PCIE 1 / 2 / 3 / 4
  • Ethernet – RGMII, SGMII, QSGMII
  • SATA 1.0/2.0/3.0
  • SDIO
  • MIPI – DSI, MIPI- CSI
  • WLAN 802.11 a/b/p/g
  • H264 Decoders
  • SPI, UART, I2C, I2X, CAN,LIN
  • AXI, AHB, APB
  • PLLs, ADC, LCO, PMU

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