PHYSICAL DESIGN ENGINEER
• Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
• Experience: 4-10 Years
• Work Location: Bangalore
• Work experience with node 16nm, 14nm, 10nm, 7nm, 5nm, etc
• Experience on ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification,etc.
• Well versed with Cadence or Synopsys tools is must.
• Experience with Static Timing Analysis in Primetime or Primetime-SI is must.
• Hands-on experience in scripting languages such as PERL, TCL,etc.
• Timing closure on high-speed interfaces is a plus.
• Knowledge on Full chip Physical Design is added advantage
• Good ASIC fundamentals and problem-solving skills is preferred.
Candidate should exhibit:
• Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
• Set aggressive goals and meet/beat the commitments.
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Ability to work independently and in a team