Analog Design & Layout
In this competitive market, while launching new product in the market, we need to choose right design for client’s success. Our design team helps the product development team at every stage of VLSI engineering process.
We help the companies with their analog circuit design/ Layout services based on different requirements to develop circuit blocks or subsystems integrated into a larger customer-designed chip.
Our design team has the relevant expertise to develop innovative analog solutions, we ‘re able to make the trade-offs necessary to optimize the design performance, area, power, time to market, product reliability, and cost of your design/product.
We do have good experience in standard cell solutions, Memory solutions, IO Solutions etc.Capabilities
- Analog and mixed signal building blocks
- High precision mixed-signal circuits
- Layout with HV devices
- Full chip integration (Analog-on-top or digital-on-top)
- Integration of high power with high accuracy circuits
- Experience with CMOS, BCD and SOI
- Complete Analog Design life-cycle from specs to post-silicon validation
- Successful delivery of multiple std cell libraries from 10nm to 90 nm, including High performance, High density, 11T, 9T, 7.5T, 6T design.
Expertise
- Worked on Ips: SerDes (10, 16, 30 & 56 Gbps), DDRphy, USB 2.0, MIPIphy, and Power management
- Handled expanded portfolios of Data converters, clock circuits such as PLL, DLL & oscillators, Regulators, Bias, Bandgap references, Temperature sensors, UVLOs, etc.
- Expertise on CMOS/FinFET process node: 3nm, 5nm, 7nm, 10nm, 14nm, 22nm, 45nm, 65nm, 90nm, 130nm, 180nm ,350nm to 500nm
- Multiple full chips and IP level tape out have been done successfully with first-pass silicon
- Worked on Memory with a variety of architecture: multi-port memories, SRAM, Memory compilers, Register files & custom memories on cutting-edge technologies
- Worked on IO layouts from 250nm to 3nm technologies including GPIOs, LVCMOS, LVTTL, LVDS, DDR, etc. with an Analog/Power ring
- ESD requirements for HBM, MM, and CDM
- Std cell library development.
- Process migration for older libraries
- Std cell Characterization
- Multi-port Memory design & layout.
- Memory compilers and Register files.
- Memory Characterization.
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FAQ's
For a person who has conquered his lower self by the divine self, his own self acts as his best friend. But for that person who has not conquered his lower self, his own self acts as his worst enemy.
For a person who has conquered his lower self by the divine self, his own self acts as his best friend. But for that person who has not conquered his lower self, his own self acts as his worst enemy.
For a person who has conquered his lower self by the divine self, his own self acts as his best friend. But for that person who has not conquered his lower self, his own self acts as his worst enemy.
For a person who has conquered his lower self by the divine self, his own self acts as his best friend. But for that person who has not conquered his lower self, his own self acts as his worst enemy.