Job Description:

• Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
• Experience: 4-10 Years
• Work Location: Bangalore

 Technical Skills:

• He/she is responsible for micro-architecture design and development of CPU Subsystem or associated component IP like high performance Bus Architectures, Memory Controllers/ DDR/USB/ NVMe/PCIE interface etc.
• Micro-architecture development and implementation of complex IP and/or ASIC block, logic designs, and HDL code for IP/ASIC blocks.
• Working individually and sometimes leading other team members in delivery of RTL design for product features.
• Strong RTL design experience of IP designs for microcontrollers/ Microprocessors expected.
• Experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC, LEC
• Knowledge & experience of building on chip bus infrastructure using AHB or AXI based IPs/ Blocks

Candidate should exhibit:

• Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
• Set aggressive goals and meet/beat the commitments.
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Ability to work independently and in a team.

Apply Now

[forminator_form id="3260"]

Job Description:

• Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
• Experience: 4-10 Years
• Work Location: Bangalore

Technical Skills:

• Memory leaf cell layout development
• Migration of layout from one tech node to another
• Block and top-level integration
• Quality and timely delivery
• EM-IR, area intensive layouts, Quality checks (QC)
• Understanding of design rules for planer and FINFET CMOS technologies
• Drive multiple projects and provide necessary technical guidance to the engineers
• Experience in developing flash memories.
• Memory Layout experience in development of low power, high performance, high density SRAM memories for 5nm to 180nm technology nodes
• The candidate must have a Bachelor or Master in (EC/ME/VLSI)
• Expertise in Custom / Compiler Memory Layout
• 7nm or below FinFet technology preferred
• Understanding of DFM and DFY checks.
• Understanding of memory compiler architectures and sub blocks.
• Knowledge of scripting in PERL/Shell/TCL/Skill is a plus.
• Strong VLSI fundamentals of semiconductor devices and physics, electrical circuits, and IC Experienced with Cadence Virtuoso/XL/Advance platform and features
• Clones, Modgen, Wire assistance, Chaining, Groups and Place and Route
• Experienced with Calibre/PVS/Assura/Hercules PV tools
• Good Verbal & written communication skills

Candidate should exhibit:

• Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
• Set aggressive goals and meet/beat the commitments.
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Ability to work independently and in a team.

Apply Now

[forminator_form id="3250"]

Job Description:

• Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
• Experience: 4-10 Years
• Work Location: Bangalore

 Technical Skills:

• Custom Layout Design to execute Chip, Block, and sub-block level from circuit schematics.
• Independent Handling and Layout Design of various Analog and Mixed Signal blocks and sub-blocks of PLLs, CDRs, SerDes, LVDS, HDMI, Serial I/Os, and Other Analog Blocks like Switched Capacitor Circuits, Operational amplifiers, Comparators, Oscillators, Voltage and Current Reference circuits etc.
• Work independently, collaborating with Project Leader and design engineers.
• Responsible for the timely execution as well as overall physical design quality of the implemented circuits.
• Follow the Project Execution Plan, Project Schedule, Work Assignment and EDA tool usage plan. - Active Participation in Customer Project Reviews.
• Layout Design in technologies with feature size 0.18um, 150nm, 90nm, 65nm, 40nm CMOS, BiCMOS, SOI Process etc.

 Candidate should exhibit:

• Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
• Set aggressive goals and meet/beat the commitments.
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Ability to work independently and in a team

Apply Now

[forminator_form id="3244"]

Job Description:

• Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
• Experience: 4-10 Years
• Work Location: Bangalore

Technical Skills:
• Custom Layout Design to execute Chip, Block, and sub-block level from circuit schematics.
• Independent Handling and Layout Design of various Analog and Mixed Signal blocks and sub-blocks of PLLs, CDRs, SerDes, LVDS, HDMI, Serial I/Os, and Other Analog Blocks like Switched Capacitor Circuits, Operational amplifiers, Comparators, Oscillators, Voltage and Current Reference circuits etc.
• Work independently, collaborating with Project Leader and design engineers.
• Responsible for the timely execution as well as overall physical design quality of the implemented circuits.
• Follow the Project Execution Plan, Project Schedule, Work Assignment and EDA tool usage plan. - Active Participation in Customer Project Reviews.
• Layout Design in technologies with feature size 0.18um, 150nm, 90nm, 65nm, 40nm CMOS, BiCMOS, SOI Process etc.

Candidate should exhibit:
• Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
• Set aggressive goals and meet/beat the commitments.
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Ability to work independently and in a team

Apply Now

[forminator_form id="2908"]

Job Description:

• Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
• Experience: 4-10 Years
• Work Location: Bangalore

Technical Skills:
• Work experience with node 16nm, 14nm, 10nm, 7nm, 5nm, etc
• Experience on ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification,etc.
• Well versed with Cadence or Synopsys tools is must.
• Experience with Static Timing Analysis in Primetime or Primetime-SI is must.
• Hands-on experience in scripting languages such as PERL, TCL,etc.
• Timing closure on high-speed interfaces is a plus.
• Knowledge on Full chip Physical Design is added advantage
• Good ASIC fundamentals and problem-solving skills is preferred.

Candidate should exhibit:
• Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
• Set aggressive goals and meet/beat the commitments.
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Ability to work independently and in a team

Apply now

[forminator_form id="2916"]

Job Description:

• Educational Qualifications: BE/BTech/ME/MTech in Electronics/Electrical Engineering.
• Experience: 4-8 Years
• Work Location: Bangalore, Hyderabad

Technical Skills:
• Experience in SOC/IP/ASIC/GLS Functional Verification
• He/she will be involved in developing testbench for the block/cluster, testcases, test plans and functional and code coverage.
• Knowledge of Industry standard protocols –Ethernet, PCIE, USB, DRR3/4, AXI, AHB and low speed peripherals, etc.
• Knowledge of Clocking, Boot/Reset flows.
• Experience with System Verilog/OVM/UVM SOC development environment is must
• Experience with Low power/UPF verification techniques.
• Strong background in scripting - PERL, TCL, Python.
• Understanding of software and/or hardware validation techniques

Candidate should exhibit:
• Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
• Set aggressive goals and meet/beat the commitments.
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Ability to work independently and in a team

Apply now

[forminator_form id="2918"]